1. Field of the Invention
The present invention relates generally to integrated circuit devices; and more specifically to a technique for aligning contact openings in erasable/programmable read only memory devices.
2. Description of the Prior Art
As feature sizes and device sizes shrink for integrated circuits, relative alignment between interconnect layers becomes of critical importance. Misalignment can severely impact the functionality of a device. Misalignment beyond certain minimum tolerances can render a device partly or wholly non-operative.
To insure that contacts between interconnect layers are made properly even if a slight misalignment occurs during masking steps, extra space is usually included in a design around contacts and other conductive features. This extra retained space is known as enclosure. Enclosure sizes of up to a few tenths of a micron are typical for 0.5 to 1.0 micron feature sizes.
Enclosure requirements are not consistent with the continued shrinkage of devices. Enclosure is not related to device functionality, but is used only to ensure that misalignment errors don't cause problems with the device. When designing devices having minimum feature and device sizes, minimizing enclosure requirements can significantly impact the overall device size.
Self-alignment techniques are generally known in the art, and it is known that their use helps minimize enclosure requirements. However, the use of self-alignment techniques has been somewhat limited by device designs in current use. It would be desirable to provide a technique for fabricating integrated circuit devices which increases the number of self-aligned fabrication steps, thereby reducing enclosure requirements for the device.
High density EPROMs have regular layouts which allow for relatively small device sizes. Minimum cell sizes are important to the design of very high density EPROMs, such as one megabit devices and larger. The area penalty caused by enclosure requirements can affect overall chip size, since the individual cell sizes are so small.
It would therefore be desirable to provide a cell layout and fabrication technique for high density EPROMs which is as small as possible. Such a fabrication technique preferably includes self-aligned structures whenever possible to minimize total cell area. It is also desirable for such a technique to be compatible with current process flows in standard use.
High density EPROM designs often include a buried Vss line. This line is formed as an active region within the substrate, so that conductivity is not as high as is the case for a metal line. As device sizes shrink, shrinking the width of the Vss line can lead to high resistivities which can adversely device performance.
It is therefore further desirable to provide a device layout and fabrication technique which provides a low resistivity Vss line. It is further desirable for such a technique to be consistent with the layout of small device sizes on a high density device, and to be compatible with current cell designs and fabrication techniques.